This invention relates a digital signal arbiter which multiplexes access by two ports into a single port. The arbiter is totally digital and asynchronous.
Many electronic systems, such as computers, must resolve which of two competing inputs will receive priority. A typical case is a dual port memory controller where two asynchronous data input ports compete for access to a user-defined single port random access memory (RAM). The controller must resolve which of the two asynchronous signal inputs is the winner and gets access to RAM. The controller then signals that the other asynchronous signal input is the loser. The loser gets a busy signal to indicate it must wait for access to RAM.
It is desirable to perform this arbitration by totally digital means. Existing arbiters fall into two classes:
Synchronous arbitration using clocks. By definition, not suitable for this application where asynchronicity is required.
Asynchronous arbitration by non-linear (analog) techniques to solve the problem of meta-instability. These arbiters typically have hard-wired priority rules and imprecise guard band times during access switching. They also have the major disadvantage of including analog circuit elements.